The present invention relates to monolithic semiconductor integrated circuit structures and particularly to such structures which contain a plurality of separable circuits one or more of which may be selectively rendered operable if such circuits meet specified functionality criteria.
With the ever-increasing micro-miniaturization of integrated semiconductor circuits and the attendant increased density of such circuits, the unit cost per chip is increasing at a very rapid pace. In addition, the likelihood of processing defects rendering the chip circuit inoperative has been greatly increased. Consequently, with the advance of large scale integration, low yields have been a problem in the fabrication of semiconductor integrated circuits. Because of this problem, the art has been seeking structures and methods wherein a defect in one portion of the chip is not necessarily fatal to the whole chip, and the undamaged portion of the chip circuits may be salvaged and used. One such approach involves arranging the devices on the chip into a plurality of discrete and separable circuits. Each of these circuits occupies a given position on the chip. With this arrangement, the aim is to be able to utilize the separable circuits without defects in the case where a defect on the chip renders one or more of the circuits inoperative.
In providing such discrete and separable circuits, we have found that it is not very practical from a fabrication view to attempt to form a structure in which the discrete circuits are completely and totally isolated from each other, i.e. they have no region or metallization in common. It is much more practical to utilize chip structures in which the discrete circuits have some regions in common such as the chip substrate on which the epitaxial layer is formed, the isolation region or the body of the epitaxial layer proper. Likewise, some of the metallization, such as metallization from one or more of the voltage supplies has to be common to some of the discrete circuits in order to obtain maximum utilization of the surface area of the chip. However, in such chip structures, we are confronted with the problem of insuring that the common regions or common metallization shared by the functional and non-functional separable circuits does not affect the performance of the functional circuits during the selective use of such functional circuits during the operation of the chip.